{"data":[{"id":2,"year":"2025","title":"Information for Authors","long_description":"

The Organising Committee of EPTC2026 warmly welcome your interest in submitting your latest work for possible presentation at EPTC2026. Only new and unpublished works will be considered. Your abstract and paper will be peer-reviewed by the EPTC Technical Program Committee. Depending on the recommendations of the reviewers and the availability of oral presentation slots, your paper may be assigned for oral presentation, interactive poster presentation, or rejected. All accepted papers, both oral and interactive poster, will be published in the conference proceedings and in IEEE Xplore, provided they have been presented at the conference.<\/p>\r\n\r\n

Papers on all aspects of electronics packaging are welcome. They will be distributed over the following 12 Tracks:<\/p>\r\n\r\n

Track Topics<\/strong><\/p>\r\n\r\n

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  1. Advanced Packaging<\/strong>: Primary focus of this technical domain on packaging system, architecture and application driven topics. System-level architectures including chiplets, 2.5D\/3D\/3.5D integration, SiP, heterogeneous integration using interposers (Si, RDL, organic, SiC) and silicon bridge die; and application-driven package design (AI, HPC, automotive, HBM, RF systems), and system-level co-design. Large-format substrates processing, including panel warpage control, yield challenges, and process scalability. Advanced IC substrates, including embedded substrate solution, glass core substrate and glass interposer.<\/li>\r\n\t
  2. Assembly and Manufacturing<\/strong>: The primary focus of this technical area is process and manufacturing technologies for advanced packaging. Topics include pre-bond wafers preparation includes warpage control and mitigation , backgrinding, thin die handling dicing, plasma dicing, particle reduction process technologies and package assembly processes such as flip chip, wire bonding, thermal compression bonding (TCB), chip stacking, Chip-to-wafer (C2W) fusion\/ hybrid bonding, Additional areas of interest include board-level assembly; heat sink and spreader attachment, multi-chip and multi-package integration (SiP, MCP); flexible and printed electronics assembly; assembly yield optimization; The scope further extends Built-in self-test (BIST), burn-in, system-level testing, and high-throughput testing methodologies, which are critical to enabling advanced heterogeneous integration.<\/li>\r\n\t
  3. Electrical Simulation & Characterization<\/strong>: Signal and power integrity, high-speed and RF electrical modeling, electromagnetic simulation, and high-bandwidth interface analysis. Advanced measurement techniques for package and system-level electrical performance, including mmWave, co-packaged optics (CPO), and high-speed data communication systems. Power delivery network (PDN) design and noise suppression for large AI systems.<\/li>\r\n\t
  4. Emerging Technologies<\/strong>: Next-generation packaging for flexible and bioelectronics, MEMS\/NEMS, and wide bandgap (SiC, GaN) devices; quantum device packaging including cryogenic integration, low-loss interconnects, qubit scaling, and integration with classical control electronics; and emerging concepts such as neuromorphic and in-memory computing and novel device–package–system co-integration architectures.<\/li>\r\n\t
  5. Interconnection Technologies<\/strong>: Primary focus of this technical domain on interconnect scaling and associated design and implementation challenges that cover materials selection, new processes and equipment capabilities. 1st-level interconnects including wire bonding, flip-chip, TSV, Cu pillar, micro-bumps, thermo-compression bonding (TCB) hybrid bonding, microbump fine-pitch interconnect scaling, and advanced bumpless technologies such as C2W and W2W hybrid bonding, electrical interconnection techniques for high-density integration.<\/li>\r\n\t
  6. Materials and Processing<\/strong>: Substrates (organic core, glass core); build-up films; polymer dielectrics; embedded substrate, lead frames and PCB materials; underfills, encapsulants, and molding compounds; thermal interface materials; novel solder alloys and die-attach materials; wafer and panel-level bonding\/debonding materials; conductive adhesives; materials for harsh environments and power device packaging applications; and materials for hybrid bonding and high-power thermal management.<\/li>\r\n\t
  7. Mechanical Simulation & Characterization<\/strong>: Thermo-mechanical stress analysis; fatigue and fracture modeling; moisture sensitivity and diffusion effects; drop, shock, and vibration reliability; process-induced deformation and warpage; and physics-based lifetime prediction models for large and complex packages.<\/li>\r\n\t
  8. Optoelectronics & Display Packaging<\/strong>: Packaging for optical interconnects, fiber coupling and co-packaged optics (CPO). Silicon photonics integration includes PIC packaging, advanced coupling and laser integration, emerging non-silicon photonics platforms (InP, GaAs, SiN, polymer) and heterogenous III-V integration. Integrated electro-optical co-design, thermal and power management supporting applications such as micro\/mini LED, AR\/VR displays, and high-density optoelectronic modules.<\/li>\r\n\t
  9. Quality, Reliability & Failure Analysis<\/strong>: Reliability testing at device, package, and board levels, including accelerated life testing and qualification methodologies. Failure mechanisms such as interconnect fatigue, delamination, voiding, and hybrid bonding defects. Advanced diagnostics, inline monitoring, advanced metrology, defect inspection, and FA techniques including X-ray, acoustic, and optical methods.<\/li>\r\n\t
  10. Smart Manufacturing & Equipment Technology<\/strong>: AI\/ML-driven manufacturing, smart factories, digital twins, and advanced process control (APC). Equipment innovations for electronic packaging spanning wafer-level, panel-level, and back-end assembly & test, for yield, reliability, and performance optimization. End-to-end data analytics for yield learning, process optimization, fault detection, and predictive maintenance across the entire semiconductor manufacturing value chain.<\/li>\r\n\t
  11. Thermal Management & Characterization<\/strong>: Heat dissipation strategies; thermal simulation and measurement; cooling technologies (air, liquid, microfluidic); thermal interface optimization; high-power device cooling; and system-level thermal design for high-power applications and data center.<\/li>\r\n\t
  12. Wafer-Level & Panel-Level Packaging<\/strong>: Wafer- and panel-level processes including fan-in\/fan-out technologies, redistribution layers (RDL), micro-bumps, TSV and mega-pillars for high-density integration. High-precision pick-and-place, overlay metrology, distortion correction, and alignment control for fine-pitch integration. Test and inspection strategies across wafer-level and panel levels, including known good die (KGD) challenges for chiplet integration.<\/li>\r\n<\/ol>\r\n\r\n

    Abstract Submission Guidelines<\/strong><\/p>\r\n\r\n

    Please download the EPTC Abstracts Template available here<\/a> and use it to prepare your 700-word abstract in Word following the instructions which are given in the template. After that, convert your Word abstract into a pdf and follow the guidelines to submit your abstract.
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    \r\nEPTC uses the Conftool conference management system for submission of abstracts and manuscripts which are both called contributions. If you do not have a user account in Conftool, you need to create one before submitting your abstract by clicking     here<\/a>. However, if you have ever attended EPTC within the last 5 years, you can simply use your past credentials to log into Conftool to submit your abstract.
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    \r\nOnce in Conftool, click the “Your Submission” option and follow the instructions therein to submit your abstract. You will be required to select the Track you wish to have your paper considered for presentation. Descriptions of the Tracks are given     here<\/a>.
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    \r\nYou can opt to be considered for interactive poster presentation if you wish. You are allowed to submit at most 2 abstracts in your name if you are not a student but only one abstract if you are a student. After submission, you can return to Conftool to make any revisions to your abstract until the deadline for submission of abstracts.
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    \r\nFor students who wish to apply for the EPS Student Travel Grants, please ensure that you are the first author of the paper and tick the appropriate boxes during your abstract submission. You will be contacted separately on this matter. Immediately after submitting your abstract, please get your full paper manuscript ready as soon as possible as you will be requested to submit your manuscript of your paper earlier for evaluation.<\/p>\r\n\r\n

    Abstract Review Process<\/strong><\/p>\r\n\r\n

    The review of abstracts will be carried out through Conftool and authors will be informed of the acceptance or rejection of their abstracts by July 10, 2026<\/span><\/strong>. Whether the presentation of the paper is oral or interactive (poster) will be based on the review of the manuscript of the full paper. Upon receipt of acceptance, authors should start to prepare their manuscripts following the Manuscript Submission Guidelines given below. <\/p>\r\n\r\n

    Manuscript Submission Guidelines<\/strong><\/p>\r\n\r\n

    Please download the EPTC Manuscript Template available here<\/a> and follow the instructions therein to prepare your manuscript in English. Your manuscript must be at least 4 full pages long and not exceed 8 pages. Prepare your manuscript carefully addressing any comments on your abstract which can be viewed by logging into Conftool. After completing your manuscript, please convert it into a PDF and name it XYZ.pdf where XYZ is the 3-digit ID of your abstract assigned by Conftool. Then log into Conftool and upload your PDF manuscript. Your submission will be acknowledged by an email from Conftool.<\/p>\r\n\r\n

    Please submit your manuscript before August 31, 2026<\/strong><\/span>.<\/p>\r\n\r\n

    The manuscript which you have submitted will be treated as a draft. It will be reviewed and you are expected to revise it according to the reviewers’ comments and resubmit the final version via Conftool by the deadline for the submission of final manuscripts. The reviewers’ comments can be viewed by logging into Conftool.
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    Download Manuscript Template<\/span><\/a><\/strong><\/span><\/p>\r\n\r\n

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    Submit Manuscript<\/span><\/a><\/strong><\/span><\/p>\r\n\r\n

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    Manuscript Review Process<\/strong><\/p>\r\n\r\n

    Authors may submit their draft manuscripts through Conftool anytime between July 10, 2026 to August 31, 2026<\/strong>.<\/span> Reviewers will be assigned by the various Technical Committee Chairs for each manuscript. All the reviews should be completed by October 1, 2026<\/span><\/strong>. Whenever a review is submitted by a reviewer, Conftool will prompt the author by an email. Authors should then log into Conftool to read the reviewer’s comments and start to amend their manuscripts according to the reviewers’ comments. The final manuscript should be submitted via Conftool by October 21, 2026<\/span><\/strong>. Please name the revised manuscript using the following format: PaperID_Revised Manuscript; Example: 123_Revised Manuscript. For those manuscripts which do not require any amendments at all, you are still required to upload it again as the revised manuscript with the appropriate filename described earlier.<\/p>\r\n\r\n

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    Download Oral Presentation Template<\/span><\/a><\/strong><\/span><\/p>\r\n\r\n

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    Download Poster Template<\/span><\/a><\/strong><\/span><\/p>\r\n\r\n

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    Plagiarism Check<\/strong><\/p>\r\n\r\n

    EPTC will perform a plagiarism check on all revised manuscripts. Manuscripts with a similarity index exceeding 20% (excluding author affiliations and references) will be returned to the authors for revision. Manuscripts that do not comply with this requirement may be withdrawn from the conference program. Authors are strongly encouraged to perform a self-check before submitting the revised manuscript. EPTC reserves the right to reject manuscripts that do not meet IEEE technical and publication standards (e.g., insufficient technical content, or figures reused from previous work without citation)<\/p>\r\n\r\n

    IEEE eCopyright Form<\/strong><\/p>\r\n\r\n

    After submitting the revised manuscript, please allow up to one (1) week for the reviewers’ final assessment. If no further comments are received during this period, you may proceed to submit the IEEE electronic Copyright (eCR) form by logging into ConfTool to display your submission and clicking the “IEEE Copyright Form” link on the right side of the screen. Before submitting the eCR form, please ensure that the manuscript is final, that consent has been obtained from all co-authors, and that all required internal technical\/legal approvals have been secured.<\/p>\r\n\r\n

    Important Dates<\/strong><\/p>\r\n\r\n

    Abstract Submission Dates<\/strong><\/span><\/p>\r\n\r\n\r\n\t\r\n\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t
    Start of online abstract submission<\/td>\r\n\t\t\tMarch 31, 2026<\/td>\r\n\t\t<\/tr>\r\n\t\t
    End of abstract submission<\/td>\r\n\t\t\tJune 15, 2026<\/td>\r\n\t\t<\/tr>\r\n\t\t
    Notification of acceptance<\/td>\r\n\t\t\tJuly 10, 2026<\/td>\r\n\t\t<\/tr>\r\n\t<\/tbody>\r\n<\/table>\r\n\r\n

    Manuscript Submission Dates<\/strong><\/span><\/p>\r\n\r\n\r\n\t\r\n\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t
    Start of online manuscript submission<\/td>\r\n\t\t\tJuly 10, 2026<\/td>\r\n\t\t<\/tr>\r\n\t\t
    End of submission of manuscript<\/td>\r\n\t\t\tAugust 31, 2026<\/td>\r\n\t\t<\/tr>\r\n\t\t
    Notification of acceptance<\/td>\r\n\t\t\tOctober 1, 2026<\/td>\r\n\t\t<\/tr>\r\n\t<\/tbody>\r\n<\/table>\r\n\r\n

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     <\/p>","page_slug":"other","created_at":"2025-09-11T02:17:54.000000Z","updated_at":"2026-10-14T15:03:34.000000Z","type":"Authors"}],"success":true,"message":"Data retrieved successfully"}